1. Field of the Invention
The present invention relates to a sense amplifier for a semiconductor memory such as, e.g., an SRAM (static random access memory).
2. Description of the Related Art
As a conventional sense amplifier circuit for reading out bit-line data in a semiconductor memory, for example, a two-stage inverting sense amplifier circuit shown in FIG. 1 is used. More specifically, reference symbols BL and BL respectively denote a pair of bit lines of each column of memory cell array; SA1 and SA2, first and second sense amplifiers serving as a first stage for sensing and amplifying a potential difference between the pair of bit lines (BL and BL); and SA3, a third sense amplifier serving as a second stage for sensing and amplifying a potential difference between outputs from the first and second sense amplifiers. These first to third sense amplifiers are respectively constituted by n-channel input type CMOS differential sense amplifiers each having a p-channel current mirror load.
The first sense amplifier SA1 is constituted by n-channel input transistors (N11 and N12), the gates of which are respectively connected to the bit lines (BL and BL), and the sources of which are commonly connected to a ground potential V.sub.SS, and p-channel load transistors (P11 and P12), the sources of which are commonly connected to a power supply potential V.sub.CC, the gates of which are connected to each other, and the drains of which are respectively connected to the drains of the n-channel transistors (N11 and N12). The gate and the drain of the p-channel transistor P11 are connected to each other, and an output is extracted from the drain of the n-channel transistor N12. With this arrangement, a signal of high level "H" is output when a potential of the bit line BL is lower than a potential of the bit line BL, and a signal of low level "L" is output when the potential of the bit line BL is lower than the potential of the bit line BL. That is, the first sense amplifier SA1 is an amplifier for outputting a non-inverted BL signal.
The second sense amplifier SA2 is constituted by n-channel input transistors (N21 and N22), the gates of which are respectively connected to the bit lines (BL and BL), and the sources of which are commonly connected to the ground potential V.sub.SS, and p-channel load transistors (P21 and P22), the sources of which are commonly connected to the power supply potential V.sub.CC, the gates of which are connected to each other, and the drains of which are respectively connected to the drains of the n-channel transistors (N21 and N22). The gate and the drain of the p-channel transistor P22 are connected to each other, and an output is extracted from the drain of the n-channel transistor N22. With this arrangement, a signal of level "H" is output when a potential of the bit line BL is lower than a potential of the bit line BL. That is, the second sense amplifier SA2 is an amplifier for outputting a non-inverted BL signal.
The third sense amplifier SA3 is constituted by n-channel input transistors (N31 and N32), the gates of which are respectively connected to an output node 41 of the first sense amplifier SA1 and an output node 42 of the second sense amplifier SA2, and the sources of which are commonly connected to the ground potential V.sub.SS, and p-channel load transistors (P31 and P32), the sources of which are commonly connected to the power supply potential V.sub.CC, the gates of which are connected to each other, and the drains of which are respectively connected to the drains of the n-channel transistors (N31 and N32). The gate and drain of the p-channel transistor P32 are connected to each other, and an output is extracted from the drain of the n-channel transistor N31 (output node 43). That is, the third sense amplifier SA3 is an amplifier for outputting inverted data of data from the first sense amplifier SA1. With this arrangement, a signal of "L" level is output when the output potential from the second sense amplifier SA2 is lower than that from the first sense amplifier SA1, and a signal of "H" level is output when the output potential from the first sense amplifier SA1 is lower than that from the second sense amplifier SA2.
An operation of the two-stage inverting sense amplifier circuit will be described with reference to FIGS. 2 and 3. In read access of a memory, it is assumed that the bit lines (BL and BL) are precharged at "H" level during a precharging period. It is the assumed that "H" data is read out from a memory cell in a read mode. In this case, the potential of the bit line BL is pulled down to the V.sub.SS potential side so that a very small potential difference is generated between the bit lines BL and BL (which is kept at "H" level). As a result, the first sense amplifier SA1 outputs a signal of "H" level, and the second sense amplifier SA2 outputs a signal of "L" level, so that the third sense amplifier SA3 outputs a signal of "L" level.
In this case, taking an operation time of the first sense amplifier SA1 into consideration, a one-stage time delay occurs in an operation until the output level from the first sense amplifier SA1 is determined. More specifically, since the potential of the bit line BL at "H" level is supplied to the gate of the n-channel transistor N11 even during the precharging period, the n-channel transistor N11 is kept in an ON state. As a result, the p-channel load transistors (P11 and P12), the gates of which are connected to the drain of the n-channel transistor N11, are kept in the ON state. In contrast, the n-channel transistor N12 is turned off upon a decrease in gate potential of the n-channel transistor N12 (potential of the bit line BL). Therefore, a one-stage gate time delay occurs because of this transition to the OFF state.
Taking an operation time of the second sense amplifier SA2 into consideration, a two-stage time delay occurs in an operation until the output level from the second sense amplifier SA2 is determined. More specifically, since the potential of the bit line BL at "H" level is supplied to the gate of the n-channel transistor N21 even during the precharging period, the n-channel transistor N21 is kept in the ON state. Meanwhile, since the n-channel transistor N22 is turned off upon a decrease in gate potential of the n-channel transistor N22 (potential of the bit line BL), a one-stage time delay occurs. In addition, the n-channel transistor N22 is turned off so that the potential of the drain of the n-channel transistor N22 becomes the "H" level, and the p-channel load transistors (P21 and P22), the gates of which are connected to the drain of the n-channel transistor N22, are turned off. A one-stage time delay occurs because of this transition to the OFF state.
Taking an operation time of the third sense amplifier SA3 into consideration, a two-stage time delay occurs from an operation timing for receiving an "H" level output from the first sense amplifier SA1 and an "L" level output from the second sense amplifier SA2 to an operation timing for determining an output from the third sense amplifier SA3 as "L" level. More specifically, the n-channel transistor N31 is turned on by an "H" level input from the first sense amplifier SA1. An "L" level output is supplied from the second sense amplifier SA2. As a result, basically in the same manner as the second sense amplifier SA2, the n-channel transistor N32 and the p-channel transistors (P31 and P32) are sequentially turned off. A two-stage time delay occurs because of this transition to the OFF states of these transistors.
As a result, when "H" data is read out from a memory cell, in the operation until the two-stage inverting sense amplifier circuit outputs a signal of "L" level, the sum of the two-stage time delay by the second sense amplifier SA2 and the two-stage time delay by the third sense amplifier SA3, i.e., a total of four-stage time delay occurs.
In contrast, when "L" data is read out from a memory cell, in an operation until the two-stage sense amplifier circuit outputs a signal of "H" level, a three-stage time delay occurs. That is, when the potential of the bit line BL is pulled down to the V.sub.SS potential side to generate a very small potential difference between the bit line BL and the bit line BL (kept at "H" level), the first sense amplifier SA1 outputs a signal of "L" level. Subsequently, the second sense amplifier SA2 outputs a signal of "H" level, and the third sense amplifier SA3 outputs a signal of "H" level. In this case, taking the operation time of the first sense amplifier SA1 into consideration, the n-channel transistor N11 is turned off upon a decrease in potential of the bit line BL. A one-stage time delay occurs because of this transition. As a result, the n-channel transistor N11 is turned off, the potential of the drain becomes "H" level, and the p-channel load transistors (P11 and P12), the gates of which are connected to the drain of the n-channel transistor N11, are turned off. A one-stage time delay occurs because of this transition so that a total of two-stage time delay is occurs.
Taking the operation of the second sense amplifier SA2 into consideration, the n-channel transistor N21 is turned off upon a decrease in potential of the bit line BL. A one-stage time delay occurs because of this transition.
In the third sense amplifier SA3, the n-channel transistor N32 and the p-channel transistors (P31 and P32) are sequentially turned on by receiving the output of "H" level from the second sense amplifier SA2, and the n-channel transistor N31 is turned off by receiving the output of "L" level from the first sense amplifier SA1. As a result, a signal of "H" level is output. In this case, assuming that the above one-stage time delays are almost equal to each other, the time delay of the output of "H" level from the second sense amplifier SA2 is smaller than that of the output of "L" level from the first sense amplifier SA1 by one stage. As a result, in the third sense amplifier SA3, the turn-ON timings of the p-channel transistors (P31 and P32) and the turn-OFF timing of the n-channel transistor N31 are almost equal to each other. The apparent time delay of the operation is, therefore, one stage.
As a result, in the operation until the two-stage inverting sense amplifier circuit outputs the signal of "H" level when "L" data is read out from the memory cell the sum of the two-stage time delay by the first sense amplifier SA1 and the one-stage time delay by the third sense amplifier SA3, i.e., a total of three-stage time delay occurs.
In a two-stage inverting sense amplifier circuit as described above, in an operation, a three-stage time delay (in case of a best pass) or a four-stage time delay (in case of a worst pass) occurs. An operation speed of the sense amplifier circuit is limited by a worst-pass operation, thereby limiting a read speed of the entire memory.
The best and worst passes described above are also present in a one-stage sense amplifier circuit and a non-inverting sense amplifier circuit as well as a two-stage inverting sense amplifier circuit.
As described above, the operation speed of the conventional sense amplifier circuit is limited by the operation speed of the worst pass. Therefore, the read speed of the entire memory is limited, resulting in inconvenience.